Signal relay circuit for securing amplitude of voltage of transmitting signals

ABSTRACT

In a signal relay circuit according to the present invention, while a capacitor serves to pass an AC component of a digital signal having a first potential level and a second potential level higher than the first potential level, a first resistor and a second resistor serve to secure an amplitude of voltage of the digital signal between the first potential level and the second potential level as received from the capacitor.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention is related to a signal relay circuit forrelaying digital signals such as clock signals.

[0003] 2. Description of the Related Art

[0004] As illustrated in FIG. 1, a prior art signal relay circuitcomprises buffer IC (Integrated Circuit) 11 which receives a clocksignal from driver IC 1, serving as a signal generating unit, throughtransmission line 10 and outputs the clock signal to receiver IC 7,serving as a signal receiving unit, through transmission line 12. Thelength of the transmission line for clock signal transmission is limiteddue to the driving capacity of driver IC 1. For this reason, in the caseof the prior art signal relay circuit, buffer IC 11 is provided in themiddle of the transmission line in order to extend the transmissiondistance of the clock signal.

[0005] Common mode noise is generated in such a structure having abuffer IC in the middle of a transmission line because of athrough-current passed through the driver IC and the buffer IC. Ifcommon mode noise flows into an electric power source or a ground, thenit is likely that the malfunction of another circuit or EMI(Electromagnetic Interference) will occur. Also, the costs required forimplementing equipment such as a server system often increase by the useof such an expensive buffer IC.

[0006] Incidentally, Japanese Patent Laid-open Publication No. 170167/95discloses a structure of a level shifter for AC signals for the purposeof eliminating self-exciting oscillation, comprising a capacitor and tworesistors at the connection point between the capacitor and an inverter.

SUMMARY OF THE INVENTION

[0007] It is an object of the present invention to provide a signalrelay circuit for relaying signals without the problems relating tohigh-cost and common mode noise due to the buffer IC for relayingsignals.

[0008] The signal relay circuit of an embodiment of the presentinvention includes a capacitor provided in the middle of a transmissionline to connect a signal generating unit with a signal receiving unit, afirst resistor which is connected between a power supply and a relaypoint between the capacitor and the signal receiving unit, and a secondresistor which is connected between a ground potential and the relaypoint.

[0009] In the signal relay circuit according to the present invention,while a capacitor serves to pass an AC (Alternating Current) componentof a digital signal having a first potential level and a secondpotential level higher than the first potential level, the firstresistor and the second resistor serve to secure an amplitude of voltageof a restored digital signal between the first potential level and thesecond potential level as received from the capacitor.

[0010] The first resistor has such a resistance value that the outputcurrent passed through the first resistor is smaller than the outputcurrent of the first potential level from a signal generating unit, andthen the first potential level of the restored digital signals can bedetected by a signal receiving unit.

[0011] On the other hand, the second resistor has such a resistancevalue that the output current passing through the second resistor issmaller than a current output of the second potential level from asignal generating unit, and then the second potential level of therestored digital signals can be detected by the signal receiving unit.

[0012] Furthermore, the resistance value of the second resistor wasselected in order that the maximum value of the first potential level isnot exceeded by the voltage drop due to a leakage current that isflowing from the signal receiving unit into the ground potential, andthen the first potential level of the restored digital signals can bedetected by the signal receiving unit.

[0013] It is therefore possible, even without a buffer IC, to transmitsignals with a sufficient amplitude as secured and reduce equipmentcosts such as server system costs and the like as compared with priorart devices. Also, it is possible to reduce a through-current andinhibit the generation of common mode noise since no buffer IC isprovided in the middle of a transmission line. Because of this, theextension of the transmission line is possible which is indispensable inthe case of a multiple board system such as a server system.

[0014] The above and other objects, features and advantages of thepresent invention will become apparent from the following descriptionwith is reference to the accompanying drawings which illustrate examplesof the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a block diagram showing a prior art example of a signalrelay circuit;

[0016]FIG. 2 is a circuit diagram showing a first embodiment of thepresent invention;

[0017]FIG. 3 is a block diagram showing an exemplary structure in whichthe signal relay circuit of the present invention is not provided; and

[0018]FIG. 4 is a graphic diagram showing the received waveforms of areceiver IC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0019] As illustrated in FIG. 2, a signal relay circuit of an embodimentof the present invention includes capacitor 3 for receiving a clocksignal from driver IC 1 through transmission line 2 and generating arestored clock signal as an AC signal by the AC coupling of the clocksignal as received, and resistors 4 and 5 for adjusting the amplitude ofvoltage of the restored clock signal suitable for reception by receiverIC 7 serving as a signal receiving unit. In this embodiment of thepresent invention, the digital signal to be transmitted is the clocksignal. This clock signal comprises a low level as a first potentiallevel and a high level as a second potential level.

[0020] Transmission line 2 has its one end connected to the outputterminal of driver IC 1, and the other end connected to one terminal ofcapacitor 3 as illustrated in FIG. 2. The other terminal of capacitor 3is connected to one end of transmission line 6. The other end oftransmission line 6 is connected to the input terminal of receiver IC 7.One terminal of resistor 4 and one terminal of resistor 5 are connectedto the relay point between capacitor 3 and transmission line 6. Theother terminal of resistor 4 is connected to power supply 8, whichserves to supply the same potential as the power source potential Vcc ofreceiver IC 7, and is applied the potential Vcc. On the other hand, theother terminal of resistor 5 is connected to ground potential.

[0021] Capacitor 3 serves to eliminate the DC (Direct Current) componentof the clock signal as received from driver IC 1 through transmissionline 2.

[0022] The resistance value of resistor 4 is selected in order that thecurrent passed therethrough may be smaller than low level output currentI_(OL) from driver IC 1. This is because the low level signal as outputfrom driver IC 1 has to be transmitted to transmission line 6 throughthe above relay point. Resistance value R4 of resistor 4 satisfies thefollowing relational equation with power supply voltage Vcc and outputcurrent I_(OL),

I_(OL)>(Vcc/R4)   (1).

[0023] The resistance value of resistor 5 is selected in order that thecurrent passed therethrough may be smaller than high level outputcurrent I_(OH) from driver IC 1. This is because the high level signalas output from driver IC 1 has to be transmitted to transmission line 6through the above relay point. Resistance value R5 of resistor 5satisfies the following relational equation with voltage Vdd applied todriver IC 1 and output current I_(OH),

I_(OH)>(Vdd/R5)   (2).

[0024] Also, resistance value R5 of resistor 5 is selected to such avalue that, even if small leakage current I_(R) flows into groundpotential from the power source of receiver IC 7 through transmissionline 6, the potential at the above relay point may not be pulled up toexceed the maximum value Vrmax of the potential Vr which can be judgedby receiver IC 7 to be the low level. Resistance value R5 of resistor 5satisfies the following relational equation with Vrmax and I_(R),

Vrmax≧R5×I_(R)   (3).

[0025] From above equations (2) and (3), resistance value R5 satisfiesthe following relational equation,

(Vdd/I _(OH))<R 5≦(Vrmax/I _(R))   (4).

[0026] Furthermore, for the purpose of securing a sufficient amplitudeof voltage between the high level and the low level, voltage value Vthwhich is the middle of the amplitude of voltage has to satisfy thefollowing relational equation with resistance values R4 and R5 and powersupply voltage Vcc,

Vth=Vcc/2={R 5/(R 4+R 5)}Vcc   (5)

R4=R5   (6).

[0027] By selecting resistor 4 and resistor 5 as described above, it ispossible to avoid the attenuation of the output current of driver IC 1through transmission line 2 and transmission line 6 and enable thesignals from driver IC 1 to reach receiver IC 7.

[0028] Incidentally, transmission line 2 and transmission line 6 havethe same length.

[0029] Next, the value as set for capacitor 3 will be explained.

[0030] The capacitance value C of the capacitor is set to satisfy thefollowing relational equations,

Z ₀ ={R _(Z) ²+(1/ω² C ²)}^(1/2) (7)

C=ω ⁻¹(Z ₀ ² −R _(Z) ²)^(−1/2) (8)

[0031] where Z₀ is the impedance of transmission line 2, R_(Z) is thecombined resistance value of transmission line 2 and capacitor 3, f isthe frequency of the clock signal, and ω is the angular frequency 2 πf.

[0032] While there is no limitation to frequency f, the length oftransmission line 2 must be shorter with higher frequency f. This isbecause, if transmission line 2 is longer, the parasitic capacitance oftransmission line 2 becomes larger to increase the time required forswitching the signal input to capacitor 3 from a low level to a highlevel, and therefore the signal input to capacitor 3 cannot follow ahigh frequency.

[0033] Next, a specific example of the above configuration of the signalrelay circuit will be explained. In what follows, it is assumed thatVcc=2.5 V, Vdd=3.3 V, Vrmax=0.7 V, I_(OL)=I_(OH)=4 mA, I_(R)=1 μA, f=100MHz and impedance Z₁ of transmission line 6 is 50 Ω.

[0034] Relation R4>625 is obtained from the above equation (1) whilerelation 700K≧R5>825 is obtained from the above equation (4). Also,relation 700 K≧R5=R4>825 is obtained from the above equation (6).

[0035] Furthermore, if Z₀=50 Ω and R_(Z)=0.04 Ω as design values, thecapacitance value C of capacitor 3 is calculated as 0.32 pF from theabove equation (8).

[0036] Next, the results of experiments will be explained for comparingthe received waveforms of clock signals as received by the receiver ICthrough the signal relay circuit according to the present invention andthe corresponding received waveforms without the use of the signal relaycircuit according to the present invention. The signal relay circuitaccording to the present invention and used in the experiments had thesame configuration as described in the above specific example.

[0037] First, the exemplary configuration used in the experimentswithout the signal relay circuit according to the present invention willbe explained.

[0038]FIG. 3 is a block diagram showing the exemplary configurationwithout the signal relay circuit according to the present invention.Line length L₁₆ of transmission line 16 for connecting driver IC 1 andreceiver IC 7 has a relationship with line length L₂ of transmissionline 2 and line length L₆ of transmission line 6 in accordance with thefollowing equation,

L ₂ +L ₆=1.5×L ₁₆   (9).

[0039] It will be understood from equation (9) that the length oftransmission line 16 is about 70% of the sum of the lengths oftransmission line 2 and transmission line 6.

[0040]FIG. 4 is a graphic diagram showing the waveforms of signalsreceived by the receiver IC. The abscissa is time T while the ordinateis the amplitude of voltage V of the received waveforms. In this case,it is assumed that V₀=Vcc=2.5 V where V₀ is the amplitude of voltage ofexpected waveform D₀ which is the received waveform in the case where ahigh level signal is input to the receiver IC in an ideal condition.Also, it is assumed that the minimum level of the input potential whichcan be judged by receiver IC 7 as the high level is 2 V. Furthermore, inFIG. 4, the minimum value of the amplitude of voltage of each waveformis adjusted to agree with Vr of receiver IC 7 for the purpose offacilitating the comparison of the respective amplitude of voltages.

[0041] As illustrated in FIG. 4, in the case where the signal relaycircuit according to the present invention was not provided, amplitudeof voltage V₁ of received waveform D₁ was 50% of V₀, i.e., 1.25 V. Whenreceived waveform D₁ is considered to oscillate with center of 1.25 Vwhich is a half Vcc, the high voltage output through transmission line16 is calculated as 1.25+(1.25/2)=1.875 V, which is smaller than theabove minimum level, i.e., 2 V. For this reason, receiver IC 7 cannotdetect the high level.

[0042] Contrary to this, in the case where the signal relay circuitaccording to the present invention was used, amplitude of voltage V₂ ofreceived waveform D₂ was 2.25 V, which was a 10% attenuated level of V₀.When received waveform D₂ is considered to oscillate with center of 1.25V which is a half Vcc, the high voltage output through transmission line6 is calculated as 1.25+(2.25/2)=2.375 V, which is larger than the aboveminimum level, i.e., 2 V. For this reason, receiver IC 7 can detect thehigh level. On the other hand, the potential of the low level iscalculated as 1.25−(2.25/2)=0.125 V, which is smaller than maximum valueVrmax, i.e., 0.7 V, of potential Vr which receiver IC 7 judges to be thelow level. For this reason, receiver IC 7 can also detect the low level.

[0043] From the above results, it was confirmed that, by providing thesignal relay circuit according to the present invention in the middle ofa transmission line, receiver IC can receive an amplitude of voltagenear the expected value to secure a sufficient amplitude fortransmitting signals.

[0044] Incidentally, while power supply 8 serves to supply powerpotential Vcc of receiver IC 7, a higher potential can also be supplied.

[0045] Also, driver circuit IC 1 and receiver IC 7 may be semiconductorintegrated circuits designed in conformity with an input interfacestandard such as HSTL (High-Speed Transistor Logic), LVTTL (Low VoltageTransistor Transistor Logic), LVDS (Low Voltage Differential Signaling),ECL (Emitter-Coupled Logic), PECL (Positive Emitter-Coupled Logic) andso forth.

[0046] While a preferred embodiment of the present invention has beendescribed using specific terms, such description is for illustrativepurposes only, and it is to be understood that changes and variationsmay be made without departing from the spirit or scope of the followingclaims.

What is claimed is:
 1. A signal relay circuit for relaying a digitalsignal transmitted from a signal generating unit to a signal receivingunit and having a first potential level and a second potential levelthat is higher than said first potential level, said circuit comprising:a capacitor connected between said signal generating unit and saidsignal receiving unit for receiving digital signal, eliminating a DCcomponent from said digital signal as received, and outputting thedigital signal, from which said DC component is eliminated, to saidsignal receiving unit as a restored digital signal; a first resistorhaving one terminal connected to a power supply which pulls up thepotential of said restored digital signal as received from saidcapacitor and the other terminal connected to a relay point between saidcapacitor and said signal receiving unit, and having a resistance valuewith which a current flowing through said first resistor is smaller thanan output current of said first potential level from said signalgenerating unit; and a second resistor having one terminal connected tosaid relay point and the other terminal connected to a ground potential,and having a resistance value with which a current flowing through saidsecond resistor is smaller than an output current from said signalgenerating unit having said second potential level.
 2. The signal relaycircuit as claimed in claim 1 wherein the resistance value of saidsecond resistor is selected in order that the maximum value of saidfirst potential level is not exceeded by the voltage drop due to aleakage current that is flowing from said signal receiving unit intosaid ground potential.
 3. The signal relay circuit as claimed in claim 1wherein when the power voltage of said signal receiving unit is equal tothat of said power supply, the resistance value of said first resistoris equal to that of said second resistor.
 4. The signal relay circuit asclaimed in claim 1 wherein when a transmission line is provided betweensaid signal generating unit and said capacitor, the capacitance value Cof said capacitor is selected to satisfy the relational equation, C=ω⁻¹(Z ₀ ² −R _(Z) ²)^(−1/2) where R_(Z) is the combinational resistancevalue of said transmission line and said capacitor, Z₀ is the impedanceof said transmission line, f is the frequency of said digital signal,and ω is the angular frequency 2 πf.